PLD Implementation of All-digital Delay-Locked Loop (CROSBI ID 538579)
Prilog sa skupa u zborniku | izvorni znanstveni rad | međunarodna recenzija
Podaci o odgovornosti
Matić, Tomislav ; Švedek, Tomislav ; Herceg, Marijan
engleski
PLD Implementation of All-digital Delay-Locked Loop
An all-digital delay-locked loop (DLL) suitable for implementation in programmable logic devices (PLD) is presented in this paper. All parts of DLL are created only from discrete digital elements. A digital controlled delay line (DCDL) is made from digital controlled delay elements (DCDE) by using LCELL (basic delay elements in ALTERA). A charge pump (CP) and a loop filter (LF) in the proposed circuit are replaced with a 3-bit up/down/hold counter. The proposed DLL is implemented and tested in ALTERA PLD EPM7128SLI10.
Delay-Locked Loop; PLD; All-digital
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Podaci o prilogu
249-252.
2008.
objavljeno
Podaci o matičnoj publikaciji
Grgić, Mislav ; Grgić, Sonja
Zagreb: Hrvatsko društvo Elektronika u pomorstvu (ELMAR)
978-953-7044-08-4
1334-2630
Podaci o skupu
50th International Symposium ELMAR-2008
predavanje
10.09.2008-12.09.2008
Bratislava, Slovačka