engleski

Limit Cycle Frequency Jittering of an Asynchronous Sigma-Delta Modulator

This paper presents limit cycle frequency jittering of a first order Asynchronous Sigma-Delta Modulator (ASDM) implemented with Schmitt trigger. Particular interest is placed on a jitter of a Schmitt trigger hysteresis voltage (hysteresis jitter). Hysteresis jitter has been modeled in MATLAB&reg ; Simulink and the model simulation has been compared with measurements for first ordered ASDM. Both simulation and measurement show that ASDM model limit cycle frequency depends on the hysteresis jitter.

Asynchronous sigma-delta; jittering; Limit cycle frequency

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