engleski

Practical measurement of timing jitter contributed by a clock-and-data recovery circuit

This paper describes a measurement of high- frequency jitter contributed by a clock-and- data recovery circuit. The contributed jitter is expressed with deterministic and random jitter terms and is given for a specific bit sequence. The measurement is illustrated on two multichannel CMOS serializer/deserializer chips applicable to 10-G Ethernet, 10-G Fibre Channel, and InfiniBand at per-channel rates of 2.5 and 3.125 GBaud.

Timing jitter, Clocks, Semiconductor device noise, Phase locked loops, Circuit noise, Semiconductor device measurement, Bit error rate, Frequency, Noise shaping, Communication standards

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