engleski

Static Series-Voltage Noise Margins of CBL, CSL and CMOS

The concept of noise margin is very important in the design and application of digital logic circuits. Noise margin is the maximum spurious signal that can be accepted by the device when used in the system, whilst still operating correctly. In this work the static series-voltage noise margin of CBL (Current-Balanced Logic), CSL (Current-Steering Logic) and CMOS are determined and compared.

noise margin; static series-voltage noise margin; CBL; CSL; CMOS

nije evidentirano