engleski

Timing Reliability Evaluation of Gate Delay Faults

In this paper we consider single gate delay as part of the gate delay fault model. Experimental results are based on statistical analysis of bistables using density distribution function of the gate propagation delay, shown for gates in CMOS and TTL technology. As a part of the measuring system the interface card between fast ADC and PC is developed using the PLD technology.

time delay; measurement; reliability; logic circuit

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