engleski

LL-DPLL Loop Behaviour at Input Signal Phase Jump with Frequency Offset

Digital phase locked loop dynamic behaviour is very important parameter in many applications. Especially, it is considerable in synchronous digital systems where the parameters connected to synchronism establishing speed are basic system parameters. In this paper behaviour of a digital phase loop class, so called LL-DPLL (Lead Lag-Digital Phase Locked Loop) in dynamic conditions of synchronism establishing is analysed. The new recurrent algorithm for expected synchronisation time and mean synchronisation time determination is presented. The obtained results are presented in graphics form.

expected synchronization time; mean synchronization time; recurrent algorithm

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