engleski

Two-to-One Multiplexer in 0.35 um CMOS Technology

This paper describes simulation results and design of a two-to-one multiplexer. The two-to-one multiplexer is designed in the 0.35 &micro ; m CMOS technology from AMS. It combines two in-phase data inputs, which is achieved by a master-slave flip-flop (MS-FF) and master-slave-master flip-flop (MSM-FF) configurations. The simulations are performed for two building blocks of the two-to-one multiplexer: latch and static multiplexer. The simulations are performed prior to the extraction of parasitics and also after the extraction of parasitics from the layout. The device parameters are chosen carefully to satisfy various, very often contradictory requirements.

CMOS; multiplexer; current mode-logic

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