engleski

Problems in PLD Implementation of All-digital DLL

Problems encountered in the implementation of an all-digital delay-locked loop (DLL) in programmable logic devices (PLD) are presented. All parts of a DLL are only created by discrete digital elements. A digital controlled delay line (DCDL) consists of digital controlled delay elements (DCDE) realized by a number of LCELLs (basic delay elements in ALTERA's PLD). An analog charge pump (CP) and a loop filter (LF) in the proposed circuit are replaced with a 3-bit UP/DOWN/HOLD counter. The proposed DLL is implemented and tested in the ALTERA PLD chip EPM7128SLI10.

Programmable Logic Device (PLD); All-digital DLL; Digital Controlled Delay Line

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