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Various Approaches to Testing Metastability Failure of Input Synchronizers

In this paper we disscus the issues ralating to the metastability performance of digital logic storage elements in asynchronous system applications. We show the equations used to calculate metastable failure rate and determine metastability parameters for one stage of synchronization. Comparing various approaches to testing metastability properties of bistable logic devices, we present our experimental measurement method based on deliberately inducing metastability in edge-triggered flip-flops. Using the time search approach in provoking metastable behavior, our method enables accurate and repeatable statistical measurements, as well as automatic data acquisition for the Mean Time Between Failures ( ) characteristic. The results can help to evaluate adequate settling time after each synchronization event to achieve the required reliability of input synchronizers in digital logic circuits design.

asynchronous; synchronizer; metastability; failure analysis; mtbf; D flip-flop; propagation delay

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