engleski

Compact Capacitance Model for Drain-Induced Barrier-Lowering of Vertical SONFET

Drain-induced barrier-lowering (DIBL) of the vertical fully-depleted silicon-on-nothing (SON) FET is extracted from the compact capacitance model of the transistor in subtreshold region. In order to verify the accuracy of the compact model, the calculated DIBL values are compared with the results obtained by the twodimensional numerical device simulator Medici over a wide range of different geometrical and material parameters. The developed model fits the Medici results, especially in the long channel region, whereas accuracy drops for shorter channels.

Silicon-On-Nothing; vertical SONFET; drain-induced barrier-lowering

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