engleski

FinFET Considerations for 0.18 um Technology

Introduction of FinFETs into future CMOS technology nodes is driven by the need to suppress the short-channel effects (SCEs). More efficient use of the silicon die area is the reason for the investigation of the FinFET integration into older CMOS technologies as a supplement or even replacement of bulk devices. The integration scheme into the standard 0.18  m process is proposed and requires only two additional dedicated masks. Evaluation of the 0.18  m FinFETs is done by comparing the 100-nm and 50-nm-wide double-gate structures with the bulk devices fabricated in the same process, using the process and device simulations. The fin devices require higher body doping concentration for the targeted threshold voltage, but pocket implants are omitted since they have better electrostatic integrity. The double-gate structures with body doping in the 1-2 1018 cm-3 range, show significantly higher ION/IOFF ratio compared to the bulk devices. The 50-nm-wide structures have the best overall performance for both digital and mixed-signal applications and validate the research into FinFET integration into older CMOS technologies.

FinFET; bulk CMOS; 0.18 um technology; nitride spacer

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