engleski

The Role of Post-Layout Verification in Microprocessor Design

Nanometer technology and high chip frequency place high demand on the EDA (Electronic Design Automation) tools to reliably and efficientlly find design problems in post-layout verification process. The only way to tackle designs with over billion transistors on a single chip is to use the knowledge and skill of highly experienced engineers in constant development and improvement of layout verification tools and methodologies. The purpose of this article is to present methodology and new challenges in layout verification and reliability checks of todays microprocessor layout designs.

Microprocessor Design; Post-Layout Verification; LVS; DRC; Parasitic Extraction; Reduction; Reliability

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