engleski

High-Speed GaAs SCFL Digital Test Structures

The work presented in this paper describes the simulations performed in order to evaluate expected performance of digital cells processed in 0.5-mm GaAs MESFET technology, before these cells are measured on-chip. A number of basic SCFL digital cells (buffer, OR, XOR, AND, D-flip-flop) is simulated, as well as various ring oscillator configurations and a programmable 2/3 divider. The cells used to generate pulse signals from the sine generator and the output cells used for measurements are also characterized. The simulations show that the operation up to 3 &#8211 ; ; 5 GHz may be achieved, which is consistent with what can be expected from the fT = 20 GHz 0.5-mm GaAs MESFET technology.

GaAs; SCFL; high-speed; digital test structures

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