Limit Cycle Frequency Jittering of an Asynchronous Sigma-Delta Modulator (CROSBI ID 555753)
Prilog sa skupa u zborniku | izvorni znanstveni rad | međunarodna recenzija
Podaci o odgovornosti
Matić, Tomislav ; Švedek, Tomislav ; Herceg, Marijan
engleski
Limit Cycle Frequency Jittering of an Asynchronous Sigma-Delta Modulator
This paper presents limit cycle frequency jittering of a first order Asynchronous Sigma-Delta Modulator (ASDM) implemented with Schmitt trigger. Particular interest is placed on a jitter of a Schmitt trigger hysteresis voltage (hysteresis jitter). Hysteresis jitter has been modeled in MATLAB® ; Simulink and the model simulation has been compared with measurements for first ordered ASDM. Both simulation and measurement show that ASDM model limit cycle frequency depends on the hysteresis jitter.
Asynchronous sigma-delta; jittering; Limit cycle frequency
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Podaci o prilogu
198-201.
2009.
objavljeno
Podaci o matičnoj publikaciji
Bratislav D. Milovanović
Niš: Institute of Electrical and Electronics Engineers (IEEE)
978-1-4244-4381-9
Podaci o skupu
INTERNATIONAL Conference on Telecommunications in Modern Satellite, Cable and Broadcasting Services - TELSIKS 2009
predavanje
07.10.2009-09.10.2009
Niš, Srbija